Partial Reconfiguration – or Self Surgery
This month’s article introduced you to difference-based partial reconfiguration. It’s a practical way of changing parameters that are otherwise fixed on-the-fly. You can adjust DCM attributes, IO drive strength, and even LUT equations using this method.
As usual the full article is in Circuit Cellar magazine, this page just includes the additional information I couldn’t fit in the article! If you have a digital subscription access it online at www.gotomycc.com otherwise see www.circuitcellar.com .
Some Useful References
References from the Article
The main references I mention in the magazine:
- Digital Duct Tape by Clayton Cameron. In Xilinx XCell Journal, Issue 66. http://www.xilinx.com/publications/archives/xcell/Xcell66.pdf
- FPGA Partial Reconfiguration Goes Mainstream by John McCaskill & David Lautzenheiser. In Xilinx XCell Journal, Issue 73. http://www.xilinx.com/publications/archives/xcell/Xcell73.pdf
- Xilinx UG380. This is specific to the Spartan 6 device. http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
Using the FPGA Editor
- Be sure to check out the ‘digital duct tape’ article, then beyond that you can see http://billauer.co.il/xilinx-fpga-editor-video-tutorial-guide.html for another guide.
Spartan 6 Partial Reconfiguration
There’s a number of *extremely useful* papers talking about PR on the Spartan6. I don’t have a ‘free’ (author-posted) link for the first paper, you can access it if you’re on a university-run network normally however (e.g. from their library).
- “Advanced Partial Run-Time Reconfiguration on Spartan-6 FPGAs” by Koch et al.
- “GOAHEAD: A Partial Reconfiguration Framework” by Beckoff et al.
- “Migrating Static Systems to Partially Reconfigurable Systems on Spartan-6 FPGAs” by Beckoff et al.
Partial Reconfiguration from Other Devices
- 100 Power Tips for FPGA Designers has a bit of info on Partial Reconfiguration & the frame formats for the Virtex 5 devices: http://books.google.ca/books?id=dOlNKAcxEFUC&pg=PT174&lpg=PT174&dq=FPGA+bitstream+frame&source=bl&ots=R7H-iNFDiM&sig=3xZWDGGryh_FpK8MTCOM7bmJCLg&hl=en&sa=X&ei=Orr6UpCdG4-xsASGyoHoBA&ved=0CE8Q6AEwAw#v=onepage&q=FPGA%20bitstream%20frame&f=false
- The following has some information for the Virtix 5 devices: http://drop.isi.edu/sites/default/files/users/nsteiner/soni-2013-bitstream-fccm13.pdf
- This thesis has some information on the Virtex 3 devices: http://scholar.lib.vt.edu/theses/available/etd-12162005-144728/unrestricted/CMorford_Thesis.pdf
Bitstream Decoding Script
My bitstream decoding script is available from GitHub, see https://github.com/colinoflynn/s6-reconfig-examples/tree/master/dumpinfo
To use the Script you have to run it in Python. It assumes you’ve got a file called diffbits.rbt (generated with the -b option to bitgen).
Recreating the Example Project
This description will rely heavily on the YouTube video here:
You can get the example project files from here: https://github.com/colinoflynn/s6-reconfig-examples/tree/master/exampleproj
Some Common Errors & Warnings
9K Block RAMs have an issue with partial reconfiguration.
You’ll get the following error when you try using Bitgen:
ERROR:Bitgen:339 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, is not compatible with partial bitstreams. For more information, please reference Xilinx Answer Record 39999. ERROR:Bitgen:157 - Bitgen will terminate because of the above errors.
The fix is simple: don’t use them. How? You’ve got to add an option to “Other MAP Command-Line Arguments” that says “-convert_bram8″
Impact Doesn’t Work on Spartan 6
When I use Impact or ChipScope to load a partial reconfiguration bitstream, it doesn’t work on the Spartan 6. It seems to wipe the FPGA first, so the entire design stops working. I never found a work-around.
The Bitstream Doesn’ t Work (doesn’t change the FPGA)
This one sucks. It’s very difficult to track down, but assuming the transfer etc is all working, the issue is probably that the .bit file you’ve programmed into the FPGA differs from the one you’ve created the difference against. You must program the EXACT bitstream you generated the difference files against. If you generated the bitstream on a different computer for example it may fail – I’ve seen this when I regenerated a bitstream on a Linux & Windows computer, both with ISE 14.4. I had used the Linux computer to generate difference files, but programmed the FPGA from the Windows computer. The partial bitstreams did not work, I had to copy the Linux original bitstream over & program that in.
If in doubt regenerate the .bit file.